1. Field of the Invention
This invention generally relates to a circuit carrier and a package structure thereof, and more particularly to a circuit carrier and a package structure thereof with passive component electrode pads or passive component electrode planes.
2. Description of Related Art
As the electronic technology advances, high technology industries have evolved. Accordingly, more and more electronic products are being developed and are heading towards compact designs. Currently, a circuit carrier, such as PCB or chip carrier, is a widely used component in circuit layout. A widely used circuit carrier is a lamination of a plurality of patterned circuit layers and a plurality of dielectric layers that alternately layout. The dielectric layer is between two adjacent patterned circuit layers. The patterned circuit layers are electrically connected through the plated through holes (PTH) or vias. Because the circuit carrier has the advantages of high layout density, compact assembly and good performance, it has been widely used in package structures. In addition, when the signals are transmitted inside the circuit carrier, the passive components such as capacitors can be disposed on the circuit carrier to effectively refrain from the coupling inductance and to reduce the cross talk when the signals switch to different states, which maintain the signal transmission quality.
FIG. 1A is the top view of a conventional circuit carrier with electronic devices. Referring to FIG. 1A, the circuit carrier 100 includes a plurality of electronic devices 104 and 130 on the surface of a substrate 110. The device 104, for example, is a chip, which is disposed on the die connecting area 104a of the substrate 110. The device 130, for example, is a passive component such as capacitor, inductor or resistor, which is disposed on the passive component connecting area 130a of the substrate 110.
FIG. 1B is a top view of the passive component connecting area of FIG. 1A. FIG. 1C is the cross-sectional view of the circuit carrier with the passive component along the I–I′ line of FIG. 1A. In FIG. 1B, the passive component electrode pads 112 and 114 are disposed on the surface of the passive component connecting area 130a and consist of the outermost patterned circuit layer (not shown). A solder mask layer 120 covers the surface of the substrate 110 and has a plurality of first solder mask openings 122a and 122b. The first solder mask openings 122a and 122b respectively expose a portion of the surface of the corresponding passive component electrode pads 112 and 114 in order to form the solder mask defined (SMD) passive component electrode pads. The passive component electrode pads 112 and 114 can be used for the circuit carrier 100 to electrically connect a passive component 130.
Referring to FIG. 1C, the passive component 130 includes a plurality of electrodes 132 and 134 whose surfaces are electrically and structurally connected to the passive component electrode pads 112 and 114 via the solders 124 and 126. Further, a flux can be used to enhance the connection between the solders 124 and 126 and the passive component electrode pads 112 and 114. In addition, after the passive component 130 is disposed on the circuit carrier 100, the remaining flux on the circuit carrier 100 can be removed by a cleaning step. Then an encapsulant 128 covers the surface of the passive component 130 to form a package structure 102.
In FIG. 1C, because the passive component 130 crosses over from the circuit carrier 110 to the passive component electrode pads 112 and 114, and the gap 108 between the passive component 130 and the solder mask layer 120 is very narrow, the remaining flux in the gap 108 between the passive component 130 and the solder mask layer 120 can not be effectively removed. In addition, the encapsulant 128 also cannot be filled into the gap 108. Hence, if a subsequent high temperature process such as reflow process is applied to the circuit carrier 100 with the passive component 130, the solders 124 and 126 may flow into the gap 109 (between the encapsulant 128 and the solder mask layer 120) below the passive component 130, which will short-circuit the passive component electrode pads 112 and 114 and make the passive component ineffective. This is so-called solder bridge issue.
To resolve the this problem, the conventional art forms a second solder mask opening with a long but narrow shape (not shown) on the solder mask layer 120 between the passive component electrode pads 112 and 114 to effectively remove the flux remaining between the passive component 130 and the solder mask layer 120, which further reduces the possibility that the solders 124 and 126 flow into the gap 109. In addition, because the second solder mask opening can increase the length of the gap 109 along the passive component electrode pads 112 and 114, it would make it more difficult to connect the solders 124 and 126 even if the solders 124 and 126 flow into the gap 109. However, because the distance between the second solder mask opening and the other mask openings 122a and 122b is pretty short, manufacturing equipment with further preciseness is required to form the second solder mask opening, which increases the cost of the circuit carrier 110. Further, when the pitch D between the passive component electrode pads 112 and 114 tends toward the find pitch, it is more difficult to form the narrow-but-long second solder mask opening, or even makes the pitch D between the passive component electrode pads 112 and 114 not wide enough to form the second solder mask opening. Therefore, a new solution is desired for the second solder mask opening to avoid the solder bridge issue that causes the ineffectiveness of the passive component 130.